1. Field of the Invention
The present invention is directed in general to integrated circuit design. In one aspect, the present invention relates to design revision management using a base cell to implement Engineering Change Orders (ECOs).
2. Description of the Related Art
As design complexity and density increase, post silicon debugging and design correction can extend the design cycle, thereby reducing market window access and increasing revenue loss. In chip design, ECO is the process of inserting a logic change directly into the netlist after it has already been processed by an automatic tool, typically by inserting spare logic cells. However, it is difficult to find an ideal distribution of spare cells since a poorly placed spare cell would require long routing wires with increased propagation delay, and a poor selection of cell types would require more cells to fix the same error. To provide flexibility in the logic insertion process, programmable base cells have been proposed which are programmed at the contact and first metal layer and above to provide the required logic functionality, but such base cells have limited flexibility and associated performance limitations and costs.